A programmable logic device (PLD) is a semiconductor integrated circuit that contains logic circuitry that can be programmed to perform a host of logic functions. Characteristically, a PLD includes configurable (“soft”) logic. In a typical scenario, a designer uses electronic design automation (EDA) tools to create a design (i.e., configure the soft logic). These tools use information regarding the hardware capabilities of a given programmable logic device to help the designer implement the custom logic circuit using multiple resources available on that given programmable logic device.
An example of a PLD that may benefit from the presently disclosed design tools and techniques include a field programmable gate array (FPGA) and, particularly an FPGA configured within an integrated system on a chip (SOC). In some systems, a PLD may interface with a fixed logic device such as an application specific integrated circuit (ASIC), structured ASIC, processor, or other device. Accordingly, the soft logic of the PLD may interact with the fixed logic (or hard logic) of the ASIC. Additionally, a single device may include both hard logic and soft logic. For example, a device may include a hardened processor system (i.e., hard logic) and configurable logic (i.e., soft logic). In some systems, a PLD may communicate with a memory and/or one or more peripherals using a high-performance interconnect (HPI) such as, for example, the AXI bus from ARM Holdings. To enable proper communication between the circuitry implemented in the hard logic and the soft logic, a particular protocol may be followed.
An HPI may ordinarily be architected to assume that all peripherals have been fully validated and will return proper responses. In a PLD configured within an SOC, however, the PLD may be directly connected to a fixed logic device by way of the HPI. Since the fixed logic device designers have no control over how the end-user will program the PLD, it cannot be assumed that all logic will now return a proper interconnect response. When a malformed interconnect response is received, the default action may be to trigger a watchdog error. Such watchdog errors are “catastrophic” from the processor/software viewpoint, because they cause an immediate reset.
As a result, improved techniques to manage how a malformed response is handled in software are desirable.